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IC-NQL
13-bit Sin/D CONVERTER WITH SSI INTERFACE
Rev B1, Page 1/24 FEATURES o Resolution of up to 8192 angle steps per sine/cosine period o Binary and decimal resolution settings, e.g. 500, 512, 1000, 1024; programmable angle hysteresis o Conversion time of just 250 ns including amplifier settling o Count-safe vector follower principle, realtime system with 70 MHz sampling rate o Direct sensor connection; selectable input gain o Front-end signal conditioning features offset (8 bit), amplitude ratio (5 bit) and phase (6 bit) calibration o 250 kHz input frequency o Absolute angle output via fast SSI interface o 8-bit on-chip period counter o A QUAD B incremental outputs with selectable minimum transition distance (e.g. 0.25 s for 1 MHz at A) o Index signal processing adjustable in position and width o Fault monitoring: frequency, amplitude, configuration (CRC) o Setup via serial EEPROM o ESD protection and TTL-/CMOS-compatible outputs APPLICATIONS o Interpolator IC for position data acquisition from analog sine/cosine sensors o Optical linear/rotary encoders o MR sensor systems
PACKAGES
TSSOP20
BLOCK DIAGRAM
VDDA PSIN
+
VDD A
-
B
Z
-
SIN NSIN
+
INCREMENTAL OUTPUT
INPUT SIN
PCOS COS
COUNTER
+
CLK DATA
-
PHASE CORRECTION
ARCTAN
SSi INTERFACE
-
NCOS
SDA
+
INPUT COS
PZERO
Sin/D CONVERSION
+
SCL NZERO
-
INPUT ZERO
VDDA
IC-NQL
PERIOD COUNTER
E2PROM INTERFACE
NERR VREF
RAM VREF
GNDA GND
CONTROL LOGIC
Copyright (c) 2004, 2010 iC-Haus
http://www.ichaus.com
IC-NQL
13-bit Sin/D CONVERTER WITH SSI INTERFACE
Rev B1, Page 2/24 DESCRIPTION IC-NQL is a monolithic A/D converter which, by applying a count-safe vector follower principle, converts sine/cosine sensor signals with a selectable resolution and hysteresis into angle position data. This absolute value is output via a synchronous-serial SSI interface and trails a master clock rate of up to 4 Mbit/s. A 8-bit period counter supplements the position data with a multiturn count. At the same time any changes in output data are converted into incremental A QUAD B encoder signals. Here, the minimum transition distance can be adapted to suit the system on hand (cable length, external counter). A synchronised zero index is generated and output to Z if enabled by the PZERO and NZERO inputs. The front-end amplifiers are configured as instrumentation amplifiers, permitting sensor bridges to be directly connected without the need for external resistors. Various programmable D/A converters are available for the conditioning of sine/cosine sensor signals with regard to offset, amplitude ratio and phase errors. Front-end gain can be set in stages graded to suit all common differential sensor signals from approximately 20 mVpp to 1.5 Vpp, and also singleended sensor signals from 40 mVpp to 3 Vpp respectively. The device reads its configuration data via the serial EEPROM interface when cycling power, respectively following an undervoltage reset. The read in cycle is repeated up to three times when data correctness is not confirmed by a CRC validation. A permanent CRC error as well as the configuration phase itself is displayed at the error message output NERR by a low level signal.
IC-NQL
13-bit Sin/D CONVERTER WITH SSI INTERFACE
Rev B1, Page 3/24 CONTENTS PACKAGES ABSOLUTE MAXIMUM RATINGS THERMAL DATA ELECTRICAL CHARACTERISTICS ELECTRICAL CHARACTERISTICS: Diagrams OPERATING REQUIREMENTS: SSI INTERFACE PARAMETERS and REGISTERS SIGNAL CONDITIONING CONVERTER FUNCTIONS MAXIMUM POSSIBLE CONVERTER FREQUENCY Serial data output . . . . . . . . . . . . . . . 4 5 5 6 8 8 10 11 12 Incremental output to A, B and Z . . . . . . . INCREMENTAL SIGNALS SIGNAL MONITORING and ERROR MESSAGES TEST FUNCTIONS SSI INTERFACE Examples of SSI Data Output Formats . . . . EEPROM INTERFACE APPLICATION HINTS Principle Input Circuits . . . . . . . . . . . . . Basic Circuit . . . . . . . . . . . . . . . . . . 13 13 DESIGN REVIEW: Notes On Chip Functions 14 15
17 18 19 20 20 21 21 22 23
IC-NQL
13-bit Sin/D CONVERTER WITH SSI INTERFACE
Rev B1, Page 4/24 PACKAGES TSSOP20 (according to JEDEC Standard) PIN CONFIGURATION TSSOP20 4.4 mm, lead pitch 0.65 mm PIN FUNCTIONS No. Name Function Input Cosine + Input Cosine +5 V Supply Voltage (analog) Ground (analog) Reference Voltage Output Incremental Output A Analog signal COS+ (TMA mode) PWM signal for Offset Sine (Calib.) 7B Incremental Output B Analog signal COS- (TMA mode) PWM signal for Offset Cosine (Calib.) 8Z Output Index Z PWM signal for Phase/Ratio (Calib.) 9 GND Ground 10 VDD +5 V Supply Voltage (digital) 11 TEST Test Input 12 CLK SSI interface, clock line 13 DATA SSI interface, data output 14 SDA EEPROM interface, data line Analog signal SIN+ (TMA mode) 15 SCL EEPROM interface, clock line Analog signal SIN- (TMA mode) 16 NERR Error Input/Output, active low 17 PZERO Input Zero Signal + 18 NZERO Input Zero Signal 19 PSIN Input Sine + 20 NSIN Input Sine External connections linking VDDA to VDD and GND to GNDA are required. The test input may remain unwired or can be linked to VDD (please note the hints given by chapter Design Review regarding the signal of pin DATA). 1 2 3 4 5 6 PCOS NCOS VDDA GNDA VREF A
IC-NQL
13-bit Sin/D CONVERTER WITH SSI INTERFACE
Rev B1, Page 5/24 ABSOLUTE MAXIMUM RATINGS
These ratings do not imply operating conditions; functional operation is not guaranteed. Beyond these ratings device damage may occur. Item No. Symbol Parameter Analog Supply Voltage Digital Supply Voltage V() < VDDA + 0.3 V V() < VDD + 0.3 V Conditions Min. -0.3 -0.3 -0.3 Max. 6 6 6 V V V Unit
G001 VDDA G002 VDD G003 Vpin()
Voltage at PSIN, NSIN, PCOS, NCOS, PZERO, NZERO, VREF, NERR, SCL, SDA, CLK, DATA, A, B, Z G004 Imx(VDDA) Current in VDDA G005 Imx(GNDA) Current in GNDA G006 Imx(VDD) G008 Imx() Current in VDD Current in PSIN, NSIN, PCOS, NCOS, PZERO, NZERO, VREF, NERR, SCL, SDA, CLK, DATA, A, B, Z Pulse Current in all pins (Latch-up Strength) G007 Imx(GND) Current in GND
-50 -50 -50 -50 -10
50 50 50 50 10
mA mA mA mA mA
G009 Ilu()
according to Jedec Standard No. 78; Ta = 25 C, pulse duration to 10 s, VCC = VCCmax, VDD = VDDmax, Vlu() = (-0.5...+1.5) x Vpin()max
-100
100
mA
G010 Vd() G011 Tj G012 Ts
ESD Susceptibility at all pins Junction Temperature Storage Temperature Range
HBM 100 pF discharged through 1.5 k -40 -40
2 150 150
kV C C
THERMAL DATA
Operating Conditions: VDDA = VDD = 5 V 10 % Item No. T01 Symbol Ta Parameter Operating Ambient Temperature Range (extended temperature range of -40 to 125 C available on request) Conditions Min. -25 Typ. Max. 85 C Unit
All voltages are referenced to ground unless otherwise stated. All currents flowing into the device pins are positive; all currents flowing out of the device pins are negative.
IC-NQL
13-bit Sin/D CONVERTER WITH SSI INTERFACE
Rev B1, Page 6/24 ELECTRICAL CHARACTERISTICS
Operating Conditions: VDDA = VDD = 5 V 10 %, Tj = -40 ... 125 C, unless otherwise stated Item No. 001 002 003 004 005 006 Symbol Parameter Conditions Min. VDDA, VDD I(VDDA) I(VDD) Von Vhys Vc()hi Permissible Supply Voltage Supply Current in VDDA Supply Current in VDD Turn-on Threshold VDDA, VDD Turn-on Threshold Hysteresis Clamp Voltage hi at PSIN, NSIN, PCOS, NCOS, PZERO, NZERO, VREF Clamp Voltage lo at PSIN, NSIN, PCOS, NCOS, PZERO, NZERO, VREF, NERR, SCL, SDA, A, B, Z Clamp Voltage hi at NERR, SCL, SDA, A, B, Z Vc()hi = V() - VDDA; I() = 1 mA, other pins open I() = -1 mA, other pins open fin() = 200 kHz; A, B, Z open fin() = 200 kHz; A, B, Z open 3.2 200 0.3 1.6 4.5 Typ. Max. 5.5 15 20 4.4 V mA mA V mV V Unit
Total Device
007
Vc()lo
-1.6
-0.3
V
008
Vc()hi
Vc()hi = V() - VDD; I() = 1 mA, other pins open
0.3
1.6
V
Input Amplifiers PSIN, NSIN, PCOS, NCOS 101 Vos() Input Offset Voltage
Vin() and G() in accordance with table Gain Select; G 20 G < 20 see 101 V() = 0 V ... VDDA G() in accordance with table Gain Select G() in accordance with table Gain Select G = 80 G = 2.667 G = 80 G = 2.667
-10 -15 10 -50 95 97 230 650 4 9 -1.0 -0.5 -10 0.35
10 15
mV mV V/K
102 103 104 105 106 107
TCos Iin() GA GArel fhc SR
Input Offset Voltage Temperature Drift Input Current Gain Accuracy Gain SIN/COS Ratio Accuracy Cut-off Frequency Slew Rate
50 102 103
nA % % kHz kHz V/s V/s
Sin/D Conversion: Accuracy 201 202 203 AAabs AAabs AArel Absolute Angle Accuracy without referred to 360 input signal, G = 2.667, calibration Vin = 1.5 Vpp, HYS = 0 Absolute Angle Accuracy after calibration Relative Angle Accuracy referred to 360 input signal, HYS = 0, internal signal amplitude of 2 ... 4 Vpp referred to output signal period of A/B, G = 2.667, Vin = 1.5 Vpp, SELRES = 1024, FCTR = 0x0004 ... 0x00FF, fin < finmax (see table 14) I(VREF) = -1 mA ... +1 mA 1.0 +0.5 10 DEG DEG %
Reference Voltage VREF 801 VREF Reference Voltage 48 52 % VDDA
Oscillator A01 fosc()
Oscillator Frequency
presented at SCL with subdivision of 2048; VDDA = VDD = 5 V 10 % VDDA = VDD = 5 V VDDA = VDD = 5 V
52 60
72 -0.1 +10.6
90 83
MHz MHz %/K %/V
A02 A03
TCosc VCosc
Oscillator Frequency Temperature Drift Oscillator Frequency Power Supply Dependance
IC-NQL
13-bit Sin/D CONVERTER WITH SSI INTERFACE
Rev B1, Page 7/24 ELECTRICAL CHARACTERISTICS
Operating Conditions: VDDA = VDD = 5 V 10 %, Tj = -40 ... 125 C, unless otherwise stated Item No. B01 B02 B03 Symbol Parameter Conditions Min. Vos() Iin() Vcm() Input Offset Voltage Input Current Common-Mode Input Voltage Range V() = Vcm() V() = 0 V ... VDDA -20 -50 1.4 0 Typ. Max. 20 50 VDDA1.5 VDDA mV nA V V Unit
Zero Comparator
B04 Vdm() Differential Input Voltage Range Incremental Outputs A, B, Z SSI Interface Output DATA D01 Vs()hi Saturation Voltage hi D02 Vs()lo D03 tr() D04 tf() D05 RL() E01 E02 E03 E04 E05 E06 E07 E08 F01 F02 F03 F04 Vt()hi Vt()lo Vt()hys Ipu() fclk() tp(CLKDATA) tbusy() tidle() Vt()hi Vt()lo Vt()hys tbusy()cfg Saturation Voltage lo Rise Time Fall Time Permissible Load at A, B Threshold Voltage hi Threshold Voltage lo Hysteresis Pull-up Current in CLK Permissible Clock Frequency at CLK
Vs()hi = VDD - V(); I() = -4 mA I() = 4 mA CL() = 50 pF CL() = 50 pF TMA = 1 (calibration mode) 1
0.4 0.4 60 60
V V ns ns M
SSI Interface: Input CLK 2 0.8 Vt()hys = Vt()hi - Vt()lo V() = 0 ... VDD - 1 V 300 -240 -120 -25 4 10 0 powering up with no EEPROM 1 1.5 2 0.8 Vt()hys = Vt()hi - Vt()lo 300 5 20 I() = 4 mA V() = 0 ... VDD - 1 V CL() = 50 pF CLK = hi, no amplitude or frequeny error 10 60.7 1 -600 -300 7 100 0.45 -75 60 ms V V mV ms kHz V A ns ms ms M 50 V V mV A MHz ns
Propagation Delay: CLK edge vs. all modes, RL(SLO) 1 k DATA output Processing Time Interface Blocking Time Threshold Voltage hi Threshold Voltage lo Hysteresis Duration of Startup Configuration error free EEPROM access Write/Read Clock at SCL Saturation Voltage lo Pull-up Current Fall Time Error Signal Indication Time at NERR (lo signal)
EEPROM Interface, Control Logic: Inputs SDA, NERR
EEPROM Interface, Control Logic: Outputs SDA, SCL, NERR G01 f() G02 Vs()lo G03 Ipu() G04 ft() G05 tmin()lo G06 Tpwm() G07 RL()
Error Signal PWM Cycle Duration fosc() subdivided by 222 at NERR Permissible Load at SDA, SCL TMA = 1 (calibration mode)
IC-NQL
13-bit Sin/D CONVERTER WITH SSI INTERFACE
Rev B1, Page 8/24 ELECTRICAL CHARACTERISTICS: Diagrams
0% AArel 10%
40% 50%
60%
twhi()/T
0% AArel 10%
90% 100%
110%
Figure 1: Definition of relative angle error.
$ tMTD
Figure 2: Definition of minimum transition distance.
0.15 0.1 0.05 0 -0.05 -0.1 -0.15
0
90
180
270
360
Figure 3: Typical residual absolute angle error after calibration.
IC-NQL
13-bit Sin/D CONVERTER WITH SSI INTERFACE
Rev B1, Page 9/24 OPERATING REQUIREMENTS: SSI INTERFACE
Operating Conditions: VDD = 5 V 10 %, Ta = -25 ... 85 C; input levels lo = 0 ... 0.45 V, hi = 2.4 V ... VDD Item No. Symbol Parameter Permissible Clock Period Clock Signal Hi Level Duration Clock Signal Lo Level Duration Conditions CFGTOS = 0x01 Fig. Min. 4 4 4 250 25 25 Max. 2x ttos ttos ttos ns ns ns Unit
I001 TCLK I002 tCLKhi I003 tCLKlo
Figure 4: Timing diagram of SSI output.
IC-NQL
13-bit Sin/D CONVERTER WITH SSI INTERFACE
Rev B1, Page 10/24 PARAMETERS and REGISTERS Register Description . . . . . . . . . . . . . . . . . . . . . . . Page 10 Signal Conditioning . . . . . . . . . . . . . . . . . . . . . . . Page 11 GAIN: Gain Select SINOFFS: Offset Calibration Sine COSOFFS: Offset Calibration Cosine REFOFFS: Offset Calibration Reference RATIO: Amplitude Calibration PHASE: Phase Calibration Converter Function . . . . . . . . . . . . . . . . . . . . . . . . Page 12 SELRES: Resolution HYS: Hysteresis FCTR: Max. Permissible Converter Frequency Incremental Signals . . . . . . . . . . . . . . . . . . . . . . . Page 15 CFGABZ: Output A, B, Z ROT: Direction of Rotation CBZ: Period Counter Configuration ENRESDEL: Output Turn-On Delay OVERVIEW Adr
0x00 0x01 0x02 0x03 0x04 0x05 0x06 0x07 0x08 0x09 0x0A 0x0B 0x0C 0x0D 0x0E 0x0F Note 0 0 0 0 0 0 0 0 0 PHASE(5:0) 0 0 0 0 0 0 SELAMPL 0 0 0 0 0 0 0 0 0 GAIN(3:0) SINOFFS(7:0) COSOFFS(7:0) REFOFFS RATIO(4) 0 0 AMPL(1:0) 0 CFGTOS(1:0) 0 0 ENRESDEL CFGSSI(1:0)
ZPOS: CFGZ: CFGAB:
Zero Signal Position Zero Signal Length Zero Signal Logic
Signal Monitoring and Error Messages . . . . . . . . . . . . . . . . . . . . . . . Page 17 SELAMPL: Amplitude Monitoring, function AMPL: Amplitude Monitoring, thresholds AERR: Amplitude Error FERR: Frequency Error Test Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Page 18 TMODE: Test Mode TMA: Analog Test Mode SSI Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Page 19 CFGTOS: Interface Timeout M2S: Period Counter Output CFGSSI: SSI Output Options
Bit 7
0
Bit 6
M2S(1:0) HYS(2:0) 1
Bit 5
Bit 4
Bit 3
Bit 2
SELRES(4:0) ZPOS(4:0)
Bit 1
Bit 0
ROT
CBZ 0 FCTR(7:0)
CFGABZ(1:0) 0
CFGZ(1:0) AERR FERR
CFGAB(1:0)
FCTR(14:8) TMODE(2:0) 0 RATIO(3:0) 0 TMA 0
CRC(7:0) check sum over address 0x00-0x0E with CRC polynomial: "100100111" (read out of EEPROM) Registers not in use must be set to zero unless otherwise noted.
Table 5: Register layout
IC-NQL
13-bit Sin/D CONVERTER WITH SSI INTERFACE
Rev B1, Page 11/24 SIGNAL CONDITIONING Input stages SIN and COS are configured as instrumentation amplifiers. The amplifier gain must be selected in accordance with the sensor signal level and
GAIN Adr 0x08, Bit 7:4 Sine/Cosine Input Signal Levels Vin() Amplitude Average value (DC) Single-ended Differential Single-ended up to 100 mVpp 0.7 V ... VDDA - 1.2 V 0.8 V ... VDDA - 1.2 V up to 120 mVpp 0.7 V ... VDDA - 1.2 V 0.8 V ... VDDA - 1.2 V up to 0.15 Vpp 0.7 V ... VDDA - 1.2 V 0.8 V ... VDDA - 1.2 V up to 0.2 Vpp 1.2 V ... VDDA - 1.2 V 1.3 V ... VDDA - 1.3 V up to 0.24 Vpp 1.2 V ... VDDA - 1.2 V 1.3 V ... VDDA - 1.3 V up to 0.28 Vpp 0.7 V ... VDDA - 1.2 V 0.8 V ... VDDA - 1.3 V up to 0.3 Vpp 1.2 V ... VDDA - 1.2 V 1.3 V ... VDDA - 1.3 V up to 0.4 Vpp 0.7 V ... VDDA - 1.2 V 0.8 V ... VDDA - 1.3 V up to 0.56 Vpp 1.2 V ... VDDA - 1.3 V 1.4 V ... VDDA - 1.4 V up to 0.8 Vpp 1.2 V ... VDDA - 1.3 V 1.4 V ... VDDA - 1.5 V up to 1 Vpp 0.8 V ... VDDA - 1.4 V 1.0 V ... VDDA - 1.6 V up to 1.2 Vpp 0.8 V ... VDDA - 1.4 V 1.1 V ... VDDA - 1.7 V up to 1.5 Vpp 0.9 V ... VDDA - 1.5 V 1.3 V ... VDDA - 1.9 V up to 2 Vpp 1.2 V ... VDDA - 1.6 V 1.7 V ... VDDA - 2.1 V up to 2.4 Vpp 1.2 V ... VDDA - 1.7 V 1.8 V ... VDDA - 2.3 V up to 3 Vpp 1.3 V ... VDDA - 1.8 V 2.0 V ... VDDA - 2.6 V
programmed to register GAIN according to the following table. Half of the supply voltage is output to VREF as center voltage to help DC level adaptation.
Code 0x0F 0x0E 0x0D 0x0C 0x0B 0x0A 0x09 0x08 0x07 0x06 0x05 0x04 0x03 0x02 0x01 0x00
Amplification 80.000 66.667 53.333 40.000 33.333 28.571 26.667 20.000 14.287 10.000 8.000 6.667 5.333 4.000 3.333 2.667
Differential up to 50 mVpp up to 60 mVpp up to 75 mVpp up to 0.1 Vpp up to 0.12 Vpp up to 0.14 Vpp up to 0.15 Vpp up to 0.2 Vpp up to 0.28 Vpp up to 0.4 Vpp up to 0.5 Vpp up to 0.6 Vpp up to 0.75 Vpp up to 1 Vpp up to 1.2 Vpp up to 1.5 Vpp
Table 6: Gain Select
SINOFFS COSOFFS Code 0x00 0x01 ... 0x7F 0x80 0x81 ... 0xFF Notes Adr 0x09, Bit 7:0 Adr 0x0A, Bit 7:0 Output Offset 0V -7.8125 mV ... -0.9922 V 0V +7,8125 mV ... +0.9922 V RATIO Code Input Offset 0V -7.8125* mV / GAIN ... -0.9922 V / GAIN 0V +7.8125 mV / GAIN ... +0.9922 V / GAIN 0x00 0x01 ... 0x0F Adr 0x0B, Bit 0, Adr 0x08, Bit 3:0 COS / SIN Code COS / SIN 1.0000 1.0067 ... 1.1 0x10 0x11 ... 0x1F 1.0000 0.9933 ... 0.9000
Table 9: Amplitude Calibration
PHASE Code 0x00 0x01 ... 0x12 ... 0x1F Adr 0x0B, Bit 7:2 Phase Shift Code 90 90.703125 ... 102.65625 102.65625 102.65625 0x20 0x21 ... 0x32 ... 0x3F
Phase Shift 90 89.296875 ... 77.34375 77.34375 77.34375
*) With REFOFFS = 0x00 und VDDA = 5 V.
Table 7: Offset Calibration Sine/Cosine
REFOFFS Code 0x00 0x01 Adr 0x0B, Bit 1 Reference Voltage Depending on VDDA (example of application: MR sensors) Not depending on VDDA (example of application: Sin/Cos encoders)
Table 10: Phase Calibration
Table 8: Offset Calibration Reference
IC-NQL
13-bit Sin/D CONVERTER WITH SSI INTERFACE
Rev B1, Page 12/24 CONVERTER FUNCTIONS
SELRES Code Adr 0x00, Bit 4:0 Binary Examples of Permissible Resolutions Input Frequencies finmax (FCTR 0x0004, 0x4304) 8192 4096 2048 1024 512 256 128 64 32 16 8 SELRES Code Adr 0x00, Bit 4:0 Decimal Examples of Permissible Resolutions Input Frequencies finmax (FCTR 0x0004, 0x4304) 2000 1600 1000 800 500 400 250 *1 125 *1,2 320 160 *2 80 *4 40 *8 200 100 *2 50 *1,4 25 *1,8
*1 *2,4,8
0x00 0x01 0x02 0x03 0x04 0x05 0x06 0x07 0x08 0x09 0x0A 0x0B 0x0C 0x0D 0x0E 0x0F
158 Hz, 635 Hz 317 Hz, 1.27 kHz 634 Hz, 2.54 kHz 1.27 kHz, 5.1 kHz 2.54 kHz, 10.2 kHz 5.1 kHz, 20.3 kHz 10.2 kHz, 40.6 kHz 20.3 kHz, 81.3 kHz 40.6 kHz, 162.5 kHz 81.3 kHz (max. 250 kHz @ 0x4202) 162 kHz (max. 250 kHz @ 0x4102)
0x10 0x11 0x12 0x13 0x14 0x15 0x16 0x17 0x18 0x19 0x1A 0x1B 0x1C 0x1D 0x1E 0x1F Notes
650 Hz, 2.6 kHz 812 Hz, 3.3 kHz 1.3 kHz, 5.2 kHz 1.6 kHz, 6.5 kHz 2.6 kHz, 10.4 kHz 3.2 kHz, 13 kHz 5.2 kHz, 20.8 kHz 5.2 kHz, 20.8 kHz 4.1 kHz, 16.3 kHz 4.1 kHz, 16.3 kHz 4.1 kHz, 16.3 kHz 4.1 kHz, 16.3 kHz 6.5 kHz, 26 kHz 6.5 kHz, 26 kHz 6.5 kHz, 26 kHz 6.5 kHz, 26 kHz
Table 11: Binary Resolutions
Not useful with incremental A quad B output. The internal converter resolution is higher by a factor of 2, 4 or 8.
Table 12: Decimal Resolutions
HYS Code 0x00 0x01 0x02 0x03 0x04 0x05 0x06 0x07 Adr 0x01, Bit 7:5 Hysteresis in Hysteresis in degree LSB 0 0.0879 0.1758 0.3516 0.7031 1.4063 5.625 45 1 LSB @ 12 bit 1/2 LSB @ 10 bit 1 LSB @ 10 bit 1/2 LSB @ 8 bit 1 LSB @ 8 bit only recommended for calibration 0.044 0.088 0.176 0.352 0.703 2.813 22.5 Absolute Angle Error*
Notes
*) The absolute angle error is equivalent to one half the angle hysteresis
Table 13: Hysteresis
IC-NQL
13-bit Sin/D CONVERTER WITH SSI INTERFACE
Rev B1, Page 13/24 MAXIMUM POSSIBLE CONVERTER FREQUENCY The converter frequency automatically adjusts to the value necessary for the input frequency and resolution. This value ranges from zero to a maximum dependent on the oscillator frequency which can be set using register FCTR. Serial data output For SSI output the maximum possible converter frequency can be adjusted to suit the maximum input frequency; an automatic converter resolution step-down feature can be enabled via the FCTR register. Should the input frequency exceed the frequency limit of the selected converter resolution, the LSB is kept stable and not resolved any further; the interpolation resolution halves. If the next frequency limit is overshot, the LSB and the LSB+1 are kept stable and so on. When the input frequency again sinks below this frequency limit, the fine resolution automatically returns.
Examples* finmax [kHz] at resol. 8192 1024 200 0.16 1.27 6.5 0.26 2.1 10.8 0.53 4.2 21.6 0.64 5.1 26.0 1.1 8.5 2.1 16.9 4.2 33.8 8.5 67.7 16.9 135 33.8 250 67.7 135 -
Max. Possible Converter Frequency For Serial Data Output Resolution Protocol Max. Input Frequency Restrictions Requirements at high input frequency FCTR Min. Res. bin dec SSI finmax 0x0004 X X X f(OSC)min / 40 / Resolution - 0x4102 8 X X X f(OSC)min / 24 / Resolution Rel. angle error 2x increased 0x4202 16 X X X 2 x f(OSC)min / 24 / Res. Rel. angle error 4x increased 0x4304 32 X X X 4 x f(OSC)min / 40 / Res. Rel. angle error 8x increased 0x4602 64 X X 4 x f(OSC)min / 24 / Res. Resolution lowered by factor of 2 0x4A02 128 X X 8 x f(OSC)min / 24 / Res. Res. lowered by factor of 2-4 0x4E02 256 X X 16 x f(OSC)min / 24 / Res. Res. lowered by factor of 2-8 0x5202 512 X X 32 x f(OSC)min / 24 / Res. Res. lowered by factor of 2-16 0x5602 1024 X X 64 x f(OSC)min / 24 / Res. Res. lowered by factor of 2-32 0x5A02 2048 X X 128 x f(OSC)min / 24 / Res. Res. lowered by factor of 2-64 0x5E02 4096 X X 256 x f(OSC)min / 24 / Res. Res. lowered by factor of 2-128 0x6202 8192 X X 512 x f(OSC)min / 24 / Res. Res. lowered by factor of 2-256 Notes *) Calculated with fosc()min taken from Electrical Characteristics item A01.
Table 14: Maximum converter frequency for serial data output.
IC-NQL
13-bit Sin/D CONVERTER WITH SSI INTERFACE
Rev B1, Page 14/24 Incremental output to A, B and Z There are two criteria which must be considered when setting the maximum possible converter frequency via the FCTR register: 1. The maximum input frequency 2. System limitations, e.g. due to slow counters or cable transmission nals. A digital zero-delay glitch filter then takes care of a temporal edge-to-edge separation, guaranteeing spike-free output signals after an ESD impact to the sensor, for instance. A serial data output is simultaneously possible at any time. However, for the transfer of angle data to the output register the incremental output is halted for one period of the clock signal applied to pin CLK.
When facing system limitations it is useful to preselect a minimum transition distance for the output sig1. Max. Possible Converter Frequency Defined By The Maximum Input Frequency Output Frequency Resolution Maximum Input Frequency Restrictions fout @ finmax Requirem. at high input frequency FCTR A, B bin dec finmax 0x0004 325 kHz X X f(OCS)min / 40 / Resolution None 0x4102 542 kHz X X f(OSC)min / 24 / Resolution Relative angle error 2x increased 0x4202 1.08 MHz X X 2 x f(OSC)min / 24 Res. Relative angle error 4x increased 0x4304 1.3 MHz X X 4 x f(OSC)min / 40 / Res. Relative angle error 8x increased Notes *) Calculated with fosc()min taken from Electrical Characteristics item A01. Examples* finmax [kHz] at resol. 8192 1024 200 0.16 1.27 6.5 0.26 2.1 10.8 0.53 4.2 21.6 0.64 5.1 26.0
Table 15: Max. converter frequency for incremental A/B/Z output, defined by the max. input frequency
2. Max. Possible Converter Frequency Defined By The Minimum Transition Distance Output Frequency Resolution Minimum Transition Distance Restrictions Example* fout @ tMTD Requirem. at A, B at high input frequency tMTD [sec] FCTR A, B bin dec tMTD 0x00FF 10 kHz X X 2048 / f(OSC)max None 22.8 0x00FE 10.05 kHz X X 2040 / f(OSC)max None 22.7 0x00FD 10.09 kHz X X 2032 / f(OSC)max None 22.6 ... ... ... ... ... ... ... 0x0006 366 kHz X X 56 / f(OSC)max None 0.62 0x0005 427 kHz X X 48 / f(OSC)max None 0.53 0x0004 512 kHz X X 40 / f(OSC)max None 0.44 0x4102 854 kHz X X 24 / f(OSC)max Relative angle error 2x increased 0.27 0x4202 1.7 MHz X X 12 / f(OSC)max Relative angle error 4x increased 0.13 0x4304 2.1 MHz X X 10 / f(OSC)max Relative angle error 8x increased 0.11 Notes *) Calculated with fosc()max taken from El.Char. item A01; the min. transition distance refers to output A vs. output B without reversing the sense of rotation.
Table 16: Max. converter frequency for incremental A/B/Z output, defined by the min. transition distance
IC-NQL
13-bit Sin/D CONVERTER WITH SSI INTERFACE
Rev B1, Page 15/24 INCREMENTAL SIGNALS
CFGABZ Code 0x00 0x01 0x02
Adr 0x02, Bit 3:2 Mode Normal Control signals for external period counters Calibration mode
Pin A A CA
Pin B B CB
Pin Z Z CZ
OFFS SIN
OFFS COS 1.1 0.9
PHASE 1.1 0.9
The following settings are required additionally: SELRES = 0x0D ZPOS = 0x00 HYS = 0x07 ROT = 0x00 AERR = 0x00 0x03 Calibration mode
+...V -...V
Figure 5: Offset
SIN*
OFFS SIN
Figure 6: Offset
COS*
OFFS COS 1.1 0.9
Figure 7: Phase*
RATIO 1.1 0.9
The following settings are required additionally: SELRES = 0x0D ZPOS = 0x00 HYS = 0x07 ROT = 0x00 AERR = 0x00 Notes
+...V -...V
Figure 8: Offset
SIN*
Figure 9: Offset
COS*
Figure 10:
Amplitude*
*) Trimmed accurately when duty cycle is 50 %; Recommended trimming order (after selecting GAIN): Offset, Phase, Amplitude Ratio, Offset;
Table 17: Outputs A, B, Z
ROT Code 0x00 0x01 Adr 0x02, Bit 5 Direction Not inverted Inverted
SIN
Table 18: Direction of Rotation
COS
cw: F->0
CBZ Code 0x00 0x01
Adr 0x02, Bit 4 Clear by zero Disabled Enabled
FF
00 ccw: 0->F
P(7:0)
A B Z
Table 19: Reset Enable for Period Counter
-180 -90 0 90 180 Angle
ENRESDEL
Code 0x00 0x01
Adr 0x02, Bit 7 Output* Function immediately after 5 ms An external counter displays the absolute angle following power on. An external counter only displays changes vs. the initial power-on condition (moving halted to reapply power is precondition.)
Figure 11: Clear by zero function of the period counter (enabled by CBZ = 1). Example for resolution 64 (SELRES = 0x0A), zero signal at 0 (ZPOS = 0x00, CFGAB = 0x00) and the direction of rotation not inverted (ROT = 0x00, COS leads SIN).
Notes
*) Output delay after device configuration and internal reset.
Table 20: Output Turn-On Delay A, B, Z
IC-NQL
13-bit Sin/D CONVERTER WITH SSI INTERFACE
Rev B1, Page 16/24
ZPOS Code 0x00 0x08 0x10 0x18 Notes Adr 0x01, Bit 4:0 Position 0 90 180 270 The zero signal is only output if released by the input pins (for instance with PZERO = 5 V, NZERO = VREF). CFGZ Code 0x00 0x01 0x02.. 03 Adr 0x02, Bit 1:0 Length 90 180 Synchronization
Table 22: Zero Signal Length
CFGAB Code 0x00 0x01 0x02 0x03 Adr 0x03, Bit 5:4 Z = 1 for B = 1, A = 1 B = 0, A = 1 B = 1, A = 0 B = 0, A = 0
Table 21: Zero Signal Position
Table 23: Zero Signal Logic
SIN
COS
A B Z (CFGZ= 0) Z (CFGZ= 1) Z (CFGZ= 2) -180 -90 0 90 180 Angle
Figure 12: Incremental output signals for various length of the zero signal. Example for a resolution of 64 (SELRES = 0x0A), a zero signal position of 0 (ZPOS = 0x00, CFGAB = 0x00) and no reversal of the rotational sense (ROT = 0x00, COS leads SIN).
IC-NQL
13-bit Sin/D CONVERTER WITH SSI INTERFACE
Rev B1, Page 17/24 SIGNAL MONITORING and ERROR MESSAGES
SELAMPL AMPL Code 0x00 0x01 0x02 0x03 Code 0x04 0x05 0x06 0x07 Notes Adr 0x0C, Bit 2 Adr 0x0C, Bit 1:0 Max ( |Sin| , |Cos| ) Voltage threshold Vth 0.60 x VDDA 0.64 x VDDA 0.68 x VDDA 0.72 x VDDA Sin2 + Cos2 Vthmin Vthmax 0.48 0.68 x VDDA 0.56 0.76 x VDDA 0.64 0.84 x VDDA 0.72 0.92 x VDDA Output amplitude* 2.4 Vpp 3.4 Vpp 2.8 Vpp 3.8 Vpp 3.2 Vpp 4.2 Vpp 3.6 Vpp 4.6 Vpp Output amplitude* 1.4 Vpp (0.28 x VDDA) 2.0 Vpp (0.40 x VDDA) 2.6 Vpp (0.51 x VDDA) 3.1 Vpp (0.62 x VDDA)
Vpp Vth
Figure 13: Signal monitoring of minimum amplitude.
Vthmax Vthmin
*) Entries are calculated with VDDA = 5 V.
Table 24: Signal Amplitude Monitoring
Figure 14: Sin2 + Cos2 signal monitoring. Each phase in the configuration process is signaled by NERR = low; the signal is only reset following a successful CRC (cyclic redundancy check). If the data transfer from the EEPROM is faulty and the CRC unsuccessful, then the configuration phase is automatically repeated. The process aborts following a third unsuccessful attempt and the error message output remains set to low. To enable the successful diagnosis of faults other types of error are signaled at NERR using a PWM code as given in the key on the left. Two error bits are provided to enable communication via the SSI interface; these bits can decode four different types of error. If NERR is held at low by an external source, such as an error message from the system, for example, this can also be verified via the SSI interface. Error events are stored for the SSI data output and deleted afterwards. Errors at NERR are displayed for a minimum of ca. 10 ms, as far as no SSI readout causes a deletion. If an error in amplitude occurs the conversion process is terminated and the incremental output signals halted. An error in amplitude rules out the possibility of an error in frequency.
AERR Code 0x00 0x01
Adr 0x03, Bit 1 Amplitude error message disabled enabled
Table 25: Amplitude Error
FERR Code 0x00 0x01 Note Adr 0x03, Bit 0 Excessive frequency error message disabled enabled Input frequency monitoring is operational for resolutions 16
Table 26: Frequency Error
Configuration Error Messaging always released
Table 27: Configuration Error
Error Keys Failure Mode No error Amplitude error Frequency error Configuration Undervoltage System error
Pin NERR HI LO/HI = 75 % (AERR = 0: HI) LO/HI = 50 % (FERR = 0: HI) LO LO NERR = low caused by an external error signal
Error bits E1, E0 with SSI 11 01 (11) 10 (11) 00 00 00
Table 28: Error Keys
IC-NQL
13-bit Sin/D CONVERTER WITH SSI INTERFACE
Rev B1, Page 18/24 TEST FUNCTIONS
TMODE Code 0x00 0x01 0x02 0x03 0x04 0x05 0x06 0x07 Condition Adr 0x06, Bit 3:1 Signal at Z Z A xor B ENCLK NLOCK CLK DIVC PZERO - NZERO TP CFGABZ = 0x00 TMA Code 0x00 0x01 Notes Adr 0x06, Bit 0 Pin A Pin B A COS+ B COS-
Description no test mode Output A EXOR B iC-Haus device test iC-Haus device test iC-Haus device test iC-Haus device test iC-Haus device test iC-Haus device test
Pin SDA SDA SIN+
Pin SCL SCL SIN-
To permit the verification of GAIN and OFFSET settings, the input amplifier outputs are available at the pins. To operate the converter a signal of 4 Vpp is the ideal here and should not be exceeded. Pin loads above 1 M are adviceable for accurate measurements.
Table 30: Analog Test Mode
Table 29: Test Mode Parameter GAIN ideally adjusts the signal levels to ca. 4 Vpp and should not be touched afterwards.
5V A: COS+ SDA: Sin+
Both scope display modes are feasible for OFFS (positive values) or RATIO adjustments; regarding the adjustment of PHASE the X/Y mode may be preferred. For OFFS adjustment towards negative values the test signals COS- (pin B) and SIN- (pin SCL) are relevant.
0V
Y/T 1 V/Div vert.
X/Y 1 V/Div vert. 1 V/Div hor.
Figure 15: Calibrated signals with TMA mode.
IC-NQL
13-bit Sin/D CONVERTER WITH SSI INTERFACE
Rev B1, Page 19/24 SSI INTERFACE After each communication cycle the SSI interface returns to its idle state when the monoflop timeout ttos has elapsed. This temporal condition also determines up to which clock line pause duration the IC-NQL retains the current data output cycle - the master may thus not undershoot a minimum clock frequency of f(CLK)min.
Signal Names Name Description P S E Stop Period counter (P7 is MSB) Sensor data (S0 is LSB) Error messages Low signal
Table 32: Signal Names
CFGTOS Code 0x00 0x01 0x02 0x03 Note Adr 0x06, Bit 5:4 Timeout ttos Ref. clock counts typ. typ. typ. typ. 128 s 16 s 4 s 1 s 256-259 32-35 8-11 2-5
f(CLK) min* 11 kHz 88 kHz 352 kHz 1.41 MHz
The angle conversion is halted for one clock cycle as soon as the interface receives the first rising edge on CLK, what is the trigger signal to output updated position data. The halt duration must be taken into consideration when calculating the maximum input frequency.
M2S Code 0x00 0x01 Adr 0x00, Bit 6:5 Period Counter Output P(7:0)
32 A ref. clock count is equal to fosc (see El. Char. A01 ). *The permissible max. clock frequency is specified by item E05 .
Table 31: Monoflop Time (SSI Timeout)
CFGSSI Code 0x00 0x01 0x02 0x03
Table 33: Period Counter Output
Adr 0x03, Bit 7:6 Additional bits E1, E0, zero bit none E1, E0, zero bit none
The IC-NQL position data output contains the period counter (P) with a bit length of 0 or 8 bits (selected by M2S), the angle value (S) with a bit length of 2 to 13 bits (depending on SELRES), and up to 3 add-on bits (error messages E1 and E0 plus a zero bit). Generally, the data output is in binary format starting with the MSB.
Ring register operation no no yes yes
Table 34: SSI Output Options
IC-NQL
13-bit Sin/D CONVERTER WITH SSI INTERFACE
Rev B1, Page 20/24 Examples of SSI Data Output Formats
Output Formats SSI 13-bit SSI Res Mode Error CRC X Example 13 bit SSI
*1
T1 S9
T2 S8
T3 S7
T4... T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22 T23 T24 T25 S6 ... S0 E1 S2 E0 S1 0 0 S0
Stop Stop Stop Stop Stop Stop Stop Stop Stop Stop Stop Stop
10 bit SSI
0
0
0
0
0
0
0
0
0
0
0
0
Example
S12 S11 S10 S9 ... S3
Stop Stop Stop Stop Stop Stop Stop Stop Stop Stop Stop Stop
0 S12 S11 S10 S9 ... S3 S2 S1 S0
0
0
0
0
0 S8
0 S7
0 S6
0 S5
0 S4
0 S3
0 S2
SSI-R *2
Example
Stop S12 S11 S10 S9
0 S12 S11 S10 S9 ... S3 P7 P6 P5 S2 S1 S0 S8 E1 S7 E0 S6 0 0 P4 ... P0, S10 S9 S12, S11 S5
Stop Stop Stop Stop Stop Stop Stop Stop Stop
25-bit SSI 13 bit SSI 8 + 13 SSI bit*3 X X Example Example Configuration M2S = 0x00, CFGSSI = 0x00, unless otherwise noted. *1) CFGSSI = 0x01; *2) CFGSSI = 0x03; *3) M2S = 0x01 Legend SSI = SSI Protocol SSI-R = SSI Ring Register operation 0 S4 0 S3 0 S2 0 S1 0 S0 0 E1 0 E0 0 0 0 0
Stop
0
Table 35: Output Formats SSI
Cycle
CLK DATA
Latch P7 MSB P0 S12 LSB MSB S0 LSB Stop P7 MSB P0 S12 LSB MSB S0 LSB Stop Timeout
Figure 16: 25-bit SSI output format during ring register operation. The example displays the transmission of a 13-bit angle value headed by period counter data of 8-bit; error messages are switched off herein (SELRES = 0x03, M2S = 0x01, CFGSSI = 0x03)
EEPROM INTERFACE Serial EEPROM components permitting operation from 3.3 V to 5 V can be connected (such as 24C02, for example). When the device is switched on the memory area of bytes 0 to 15 is mapped onto IC-NQL's registers.
IC-NQL
13-bit Sin/D CONVERTER WITH SSI INTERFACE
Rev B1, Page 21/24 APPLICATION HINTS Principle Input Circuits
Figure 17: Input circuit for voltage signals of 1 Vpp with no ground reference. When grounds are not separated the connection NSIN to VREF must be omitted.
Figure 18: Input circuit for current signals of 11 A. This circuit does not permit offset calibration.
Figure 19: Input circuit for single-sided voltage or current source signals with ground reference (adaptation via resistors R3, R4).
Figure 20: Simplified input wiring for single-sided voltage signals with ground reference.
Figure 21: Input circuit for differential current sink sensor outputs, eg. using Opto Encoder iC-WG.
Figure 22: Combined input circuit for 11 A, 1 Vpp (with 120 termination) or TTL encoder signals. RS3/4 and CS1 serve as protection against ESD and transients.
IC-NQL
13-bit Sin/D CONVERTER WITH SSI INTERFACE
Rev B1, Page 22/24 Basic Circuit
Figure 23: Basic circuit for evaluation of magneto-resistor bridge sensors.
IC-NQL
13-bit Sin/D CONVERTER WITH SSI INTERFACE
Rev B1, Page 23/24 DESIGN REVIEW: Notes On Chip Functions
IC-NQL X2 IC-NQL X3 No. 1
Function, Parameter/Code ZPOS Illegal settings: 0x01...0x07, 0x09...0x0F, 0x11...0x17, 0x19...0x1F
Description and Application Hints Illegal settings of ZPOS delay accurate converter operation following power on. Depending on the sin/cos input signals (phase angle) the A/B outputs can provide pulses causing an external counter to alternately count up and down. This may disturb the startup of a drive if the motion controller tolerates only single A/B edges during standstill checking. The converter operation is again accurate when the sin/cos input signals have changed, by a maximum of 45 angular degrees.
2
M2S Illegal settings: 0x02, 0x03
Illegal settings, enabling a period counter output of 12 or 24 bits, may cause position data jumping with fast changes in the direction of count (e.g. applications with length gauges). It is thus advisable to use 8-bit period counting (M2S 0x01) and to capture the overflow in the external microcontroller. When cycling power pin DATA may show high or low level initially. With pin TEST = low (e.g. pin open) at least a single low pulse at pin CLK is required to trigger pin DATA to show a high level after the timeout has elapsed. When continuing the clock signal after completion of data output, additional zero bits are output. With pin TEST = high (e.g. pin wired to VDD) only the timeout needs to elapse to trigger pin DATA showing high level. When continuing the clock signal after completion of data output, additional one bits are output.
3
Pin DATA
Table 36: Notes on chip functions
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IC-NQL
13-bit Sin/D CONVERTER WITH SSI INTERFACE
Rev B1, Page 24/24 ORDERING INFORMATION
Type IC-NQL
Package TSSOP20 4.4 mm
Order Designation IC-NQL TSSOP20
For technical support, information about prices and terms of delivery please contact: iC-Haus GmbH Am Kuemmerling 18 D-55294 Bodenheim GERMANY Tel.: +49 (61 35) 92 92-0 Fax: +49 (61 35) 92 92-192 Web: http://www.ichaus.com E-Mail: sales@ichaus.com
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